I. Field of the Invention
This invention relates to semiconductor integrated memory circuits and more particularly to reductions in total current consumption and peak current levels during precharge operations of memory circuits.
II. Description of the Prior Art
The data capacity of semiconductor integrated memory circuits is quadrupling every two or three years, and this trend can be seen in all semiconductor integrated memory circuits including Random Access Memories (RAM) and Read Only Memories (ROM) with dynamic or static operation. However, the engineering difficulties of designing such large capacity semiconductor integrated memory circuits are staggering.
One problem is current consumption, particularly, the increase of momentary peak current during precharge operations. As the peak current increases, high frequency components in the power source potential are increasingly induced. This creates noise on some signal lines in an IC chip, which further results in misoperation and requires capacitors to absorb the noise. In a dynamic memory or a static memory with a dynamic operation, some signal lines are repeatedly precharged and discharged so that the same potential is applied to the signal lines before a read-out operation to speed up operation. The current for charging and discharging the signal lines has a momentary peak. Generally, as the memory capacity increases, the charge-discharge current increases, since stray capacitance associated with the main signal lines increases. The higher the operating speed of the memory circuit becomes, the higher the charge-discharge speed becomes and the sharper the peak current becomes.
FIG. 1 shows a static type memory cell 100 using cross-coupled N channel type enchancement mode MOS transistors 102 and 104 and high resistivity polycrystalline silicon (polysilicon) as load elements 106 and 108. Data is read out of and written into memory cell 100 through transfer gate MOS transistors 110 and 112 which selectively connect bit lines 114 and 116 with nodes 118 and 120. MOS transistors 110 and 112 are controlled by a control signal from a word line 122 for selecting memory cell 100.
FIG. 2 shows a conventional memory circuit having memory cells, as shown in FIG. 1, arranged in a matrix, with a peripheral circuit for controlling read-write operations. Memory cells 124-134 are connected with bit lines 136-142 and word lines 144-154. Balance type sense AMP circuits 156 and 158 are connected with bit lines 136-142 and are enabled by an enable signal from sense AMP enable line 160. Bit lines 136-142 are precharged to an initial level during a predetermined period of every access cycle by precharge circuits 162 and 164, as controlled by precharge control signals from precharge control line 166. A memory cell is selected by row decoder 168 and column decoder 170 which receive address signals, respectively. The bit lines, for example 136 and 138, are selected by column line 172, and are connected with common input-output lines 174 and 176 which are further connected with input-output line precharge circuit 178 and input-output circuit 180. The common input-output lines 174 and 176 are precharged by input-output line precharge circuit 178 controlled by precharge control line 182.
During the precharge operation by precharge circuits 162 and 164, sense AMP circuits 156 and 158 are not activated. Accordingly, the precharge current by precharge circuits 162 and 164 and input-output line precharge circuit 178 flows to charge only stray capacitances Ca-Cd associated with bit lines 136-142, and stray capacitances Ce and Cf associated with input-output lines 174 and 176. Generally, the values of stray capacitances Ca-Cf are large, because the memory cells are arranged in a matrix, and the larger the memory capacity, namely the number of bits, the larger the stray capacitance value becomes. Accordingly, not only the average current consumption, but also the momentary peak current to charge the large capacitances becomes large.